Circuit arrangement for operating a semiconductor memory system
US4090255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1976 |
| Grant date | May 16, 1978 |
| Priority date | — |
| Expiry date | Mar 1, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases. This is accomplished through coupling the storage cell to both read/write circuits and restore/recovery circuits via the bit lines and by selective pulsing of the cell with the read/write circuits and the restore/recovery circuits. This permits high speed, low operating current, large scale memory systems to be built.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.