Sample-and-hold circuit
US4091297A · kind A · utility
10Cited by
1References
3Claims
0Family size
Inventor
Key dates
| Filing date | Dec 8, 1975 |
| Grant date | May 23, 1978 |
| Priority date | — |
| Expiry date | Dec 8, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A unique slope-controlled crest detector and sample-and-hold circuit for determining the peak values of a fluctuating input signal and providing a control signal indicating the time of occurrence of the peak value. This circuit successfully eliminated undesirable filtering and phase delay from the data path while incorporating adequate filtering to the slope sensing circuitry to allow good operation with poor signal-to-noise ratio on the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.