Patent · US Expired

Verification technique for checking wrapped wire electronic boards

US4091325A · kind A · utility

6Cited by
4References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 8, 1977
Grant dateMay 23, 1978
Priority date
Expiry dateFeb 8, 1997

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/67
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A verification technique which greatly simplifies and facilitates the tesg of the wiring of wrapped wire electronic boards. The technique contemplates continuity testing of each branch and discontinuity testing between successive branches. After a continuity test for one branch and a discontinuity test with the next succeeding branch, the two branches are then short-circuited. The procedure is repeated with each wired branch until all branches have been tested, whereupon the short-circuit wire may then be removed. The testing technique may be facilitated by utilizing a numerically controlled terminal locator in combination with a computer generated control tape. The technique also contemplates a visual check to verify that all pins on the board that are intended to be wired are indeed wired, and that all pins on the board which are not intended to be wired are indeed bare.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.