Method of manufacturing silicon integrated circuits utilizing selectively doped oxides
US4092185A · kind A · utility
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3Claims
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Assignee
Inventor
Key dates
| Filing date | Jul 19, 1976 |
| Grant date | May 30, 1978 |
| Priority date | — |
| Expiry date | Jul 19, 1996 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/085
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming buried regions in a printed circuit substrate in which; a first layer of doped silicon oxide is deposited on the substrate, a pattern of apertures is produced in this layer and a second layer of differently doped silicon oxide is deposited to fill in apertures. The first layer silicon dioxide acts as a mask to the doping material so that when the two layers are subjected to a common diffusion step both doping materials are driven into the substrate, with the second layer doping material restricted to the regions of the apertures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.