Memory sparing arrangement
US4093985A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 1976 |
| Grant date | Jun 6, 1978 |
| Priority date | — |
| Expiry date | Nov 5, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunctioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subsequently addressed. The approach does not diminish the available system memory address range after spare module substitution. Additionally, no memory reconfiguration is required after spare module substitution except for loading of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.