Crosspoint bias circuit arrangement
US4096399A · kind A · utility
15Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1977 |
| Grant date | Jun 20, 1978 |
| Priority date | — |
| Expiry date | Mar 28, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor transmission circuit arrangement which utilizes symmetrical transmission transistors and bias circuitry which exhibits a high output impedance and is arranged to maintain equal d.c. bias currents in the base and the emitter/collectors of the transmission transistor. A multiple collector transistor is utilized as a primary current source and a current mirror circuit is used as a control arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.