Modular signal processor having a hierarchical structure
US4096566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1975 |
| Grant date | Jun 20, 1978 |
| Priority date | — |
| Expiry date | Dec 16, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.