Computer system with a memory access arbitrator
US4096572A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1976 |
| Grant date | Jun 20, 1978 |
| Priority date | — |
| Expiry date | Sep 28, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A micro-computer system includes a memory device, a plurality of memory utilization devices such as processors, a bus connected between the memory device and the memory utilization devices for address information and data transfer therebetween, bus control lines, and an access arbitrator for preventing simultaneous accesses of memory utilization devices to the memory device. The bus control lines include two lines for transferring address transfer and write/read control information from one of the memory utilization devices to the memory device and one line for coupling an access acknowledge signal from the memory device to one of the memory utilization devices. The access arbitrator couples the access acknowledge signal to one of the memory utilization devices issuing an access request signal and disables another memory utilization device to issue the address transfer and read/write control information on the two bus control lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.