Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
US4099231A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1975 |
| Grant date | Jul 4, 1978 |
| Priority date | — |
| Expiry date | Oct 1, 1995 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity. Logic in both the processor and the memory unit is initialized to acount for the words being transferred such that each word selected is stored in the proper buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.