Monitoring circuit
US4099668A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1976 |
| Grant date | Jul 11, 1978 |
| Priority date | — |
| Expiry date | Oct 29, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A monitoring circuit for digital circuits is disclosed. The monitor is primarily applicable to digital circuits which operate in a cyclic mode with the digital patterns generated during each cycle being repeated in a predictable manner. A predetermined number of expected bit patterns are stored in a programmable memory. The stored bit patterns correspond on a bit-by-bit basis to the bit patterns generated by the circuit being monitored when this circuit is operating normally. In the self-scan mode each pattern generated by the circuit being monitored is compared to each of the patterns stored in the memory in a sequential manner. Each time a pattern generated by the circuit being monitored is found to identically correspond to a pattern stored in the memory a valid pattern pulse is generated which steps a down counter one count. If this process does not result in the down counter being stepped the expected number of times during the operating cycle, a flip-flop is set indicating that the circuit being monitored has malfunctioned. Provisions are also included for counting the transitions of a digital signal during predetermined portions of the cycle of the circuit being monitored an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.