Demultiplexer for originally synchronous digital signals internested word-wise
US4101739A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 1977 |
| Grant date | Jul 18, 1978 |
| Priority date | — |
| Expiry date | Jan 14, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/1641
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A time division demultiplexer for demultiplexing synchronous digital signals which are interleaved wordwise comprising a shift register of length (m + 1) .multidot. n, where n is the number of bits/word and m is the number of interleaved signals, having a control unit and a first and second store having a total capacity of m .multidot. n bits and each having m parallel inputs and m outputs; said shift register having an output tap every n bits, said first store having m .multidot. q storage elements and said second store having m .multidot. r storage elements, where q and r are integers and q + r = n; said first store being loaded by the first q bits of m words appearing at said shift register input point and on the succeeding m - 1 of said taps counting from said input point of said shift register; said second store being loaded with the second r bits of said m words appearing at said output point and the preceding m - 1 of said taps of said shift register; said second store being loaded approximately (m .multidot. n/2) pulses after said first store is loaded; said respective outputs of said first and second stores being tied together and a first q bits of m words being read out i…
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