Circuit breaker apparatus including asymmetrical fault detector
US4104691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1976 |
| Grant date | Aug 1, 1978 |
| Priority date | — |
| Expiry date | Sep 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/093
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit breaker apparatus is taught which includes three time delayed modes of interruption and an instantaneous interruption. A long time delay mode is taught for interrupting overload current in the line to be protected. The latter time delay is inversely proportional to the square of the overload current. A short time delay mode is taught for providing a circuit breaker tripping operation after a predetermined fixed time delay when the current flowing in the line to be protected exceeds a predetermined amount. An asymmetrical fault detecting range of interruption is taught which overlaps the region of overload current which normally would require an instantaneous tripping of the circuit breaker as a function of the properties of the circuit breaker but which nevertheless delays interruption of the circuit breaker for a relatively short period of time to test subsequent peaks of the fault or overload current to determine if the latter current decays to a value which does not necessitate quick tripping of the circuit breaker during the delay period. The latter case is related to the occurrence of a fully offset asymmetrical transient fault condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.