Large delay spread channel simulator
US4105958A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1976 |
| Grant date | Aug 8, 1978 |
| Priority date | — |
| Expiry date | Feb 2, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/0087
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus for simulating the characteristics of a signal channel which uses two or more cascaded delay lines each of which in one embodiment has a single input and a plurality of tapped outputs. The tapped output signals from each delay line are each multiplied by randomly characterized signals and the multiplied signals are combined to supply an input signal to the next succeeding delay line. The input signal to the first of the cascaded delay lines is the channel input signal and the output of the last of the cascaded delay lines is the simulated channel output signal. The randomly characterized signals associated with all but one of the delay lines may be signals having random polarities or having random phases while the randomly characterized signals associated with the remaining one of the delay lines has Gaussian characteristics. Appropriate control of the amplitude of the Gaussian characterized signals permits an approximation to be made of the energy distribution of the signal channel which is being simulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.