Offset correction circuit for phase detectors
US4105975A · kind A · utility
15Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1977 |
| Grant date | Aug 8, 1978 |
| Priority date | — |
| Expiry date | Feb 1, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An offset error correction circuit for improved reception of signals by compensating for any offset error voltage produced by a phase detector in the absence of an input signal to the detector. The error correction circuit translates the offset error voltage into a digital value and stores that value in a counter. When a PSK signal is applied to the circuit, the error correction circuit subtracts the stored value of the offset error voltage from the output of the phase detector which compensates for the offset error. The compensation for the offset error provides an improved signal to noise ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.