Ratioless type MIS logic circuit
US4107548A · kind A · utility
15Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1977 |
| Grant date | Aug 15, 1978 |
| Priority date | — |
| Expiry date | Mar 4, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.