Circuit for shutting down an inverter
US4107771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1977 |
| Grant date | Aug 15, 1978 |
| Priority date | — |
| Expiry date | Feb 22, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/517
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit for shutting down an inverter that includes at least a series combination of first and second gate controlled rectifiers and a load. The circuit is comprised of means for sensing the direction and magnitude of the instantaneous current flowing through the load, and means responsive to the direction and magnitude of the sensed current for generating an output signal when the magnitude of the current exceeds a predetermined threshold level and the current is flowing in a first direction. The circuit further comprises means responsive to the simultaneous receiving of a shutdown signal and the generated output signal for further generating a gating pulse to be applied to the second gate controlled rectifier to cause the current flowing through the load to quickly extinguish. Further included is means responsive to the shutdown signal for inhibiting further regular gating of the gate controlled rectifiers to ensure quick turn off of the inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.