High speed, radiation hard complementary MOS capacitive voltage level shift circuit
US4109163A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1977 |
| Grant date | Aug 22, 1978 |
| Priority date | — |
| Expiry date | Mar 11, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09485
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A complementary MOS voltage level shift circuit which can be used as a memory buffer circuit, for example, is disclosed. The circuit utilizes both N-channel depletion mode devices and P-channel enhancement mode MOS devices preferably fabricated on silicon-on-sapphire. Both types of devices are operated with only negative or zero gate-source voltage in order to minimize threshold voltage shifts in radiation environments. A capacitive voltage level shifting technique is used to obtain push-pull operation with driver type devices in order to reduce power consumption and increase switching speed while feeding into a capacitive load. Load type devices are used to prevent discharge of a capacitive load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.