Signal strength meter drive circuit
US4109206A · kind A · utility
6Cited by
5References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1977 |
| Grant date | Aug 22, 1978 |
| Priority date | — |
| Expiry date | Jun 17, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/22
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A signal strength meter drive circuit for a radio receiver or tuner comprises a bypass resistor R.sub.3 connected in shunt with the output resistor R.sub.1 of a mirror circuit for an IF amplifier output summing transistor Q.sub.10 through a transistor Q.sub.32 whose conduction is controlled by the biasing voltage for the circuit. The mirror circuit current drawn through the bypass resistor regulates the voltage drop across the output resistor, thus compensating for variations in the voltage characteristics of the various circuit elements, such as the Zener voltage, when they are incorporated in a monolithic IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.