Method for manufacturing complementary insulated gate field effect transistors
US4110899A · kind A · utility
23Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1977 |
| Grant date | Sep 5, 1978 |
| Priority date | — |
| Expiry date | Jan 4, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.