Method of manufacturing oxide isolated semiconductor device utilizing selective etching technique
US4111724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1976 |
| Grant date | Sep 5, 1978 |
| Priority date | — |
| Expiry date | Dec 14, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.