Addressable MNOS cell for non-volatile memories
US4112507A · kind A · utility
38Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1976 |
| Grant date | Sep 5, 1978 |
| Priority date | — |
| Expiry date | Jan 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable MNOS transistor structure is disclosed employing a plurality of gate regions between the source and drain diffusion regions of each transistor cell. The transistor cell is characterized by high and low threshold states which are settable by selective actuation of the corresponding plurality of gate regions. Reading of the state of the transistor is accomplished by applying a read voltage, having a value intermediate the two threshold values, to the corresponding plurality of gate regions and measuring whether or not an applied charge discharges from one diffusion region to the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.