Fabrication methods for the high capacity ram cell
US4112575A · kind A · utility
37Cited by
3References
51Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1976 |
| Grant date | Sep 12, 1978 |
| Priority date | — |
| Expiry date | Dec 20, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a process for constructing an array of memory cells. Each cell is constructed to have a high storage capacity and low leakage current. The cells are formed on a surface of a semiconductor substrate. Each cell has a storage region and an adjacent transfer region. The process forms a deep ion layer and a shallow ion layer in the storage region of each cell. At the storage region-transfer region interface, the deep ion layer lies laterally within the shallow ion layer. In the other portions of the storage region, the deep ion layer extends laterally into adjoining channel stops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.