Noise blanker circuit
US4114105A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 1977 |
| Grant date | Sep 12, 1978 |
| Priority date | — |
| Expiry date | Jun 27, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/345
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A noise blanker circuit usable in a radio receiver is disclosed. Noise pulses in demodulated received signals are detected by a noise detector amplifier. These detected noise pulses are then processed by a control means which develops control signals that selectively control a blanking gate which is followed by a holding capacitor. The gate and holding capacitor combine to blank out noise in the demodulated signals in response to the production of the control signals. The control means includes an amplifier with an AC negative feedback loop that includes a varactor diode. A rectifier diode is used to develop a DC voltage proportional to the occurrence rate of noise pulses and this DC voltage biases the varactor diode such that noise blanking only occurs when the noise present on the received signal is below a predetermined rate of occurrence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.