Packaging of a semiconductor
US4115838A · kind A · utility
9Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1976 |
| Grant date | Sep 19, 1978 |
| Priority date | — |
| Expiry date | Aug 17, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solid state electrical component is packaged within a housing and after connection to a terminal board is potted by an encapsulating medium. The solid state electrical component includes a chip area and a plurality of terminals connected to the chip. These terminals are connected to a terminal board which provides support for additional terminal members which extend from the housing and adapted for connection in an electrical circuit. The housing and device are supported by a frame serving as a heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.