Method of making semiconductor device with PN junction in stacking-fault free zone
US4116719A · kind A · utility
26Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1977 |
| Grant date | Sep 26, 1978 |
| Priority date | — |
| Expiry date | Feb 8, 1997 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of making a semiconductor device, a semiconductor wafer having a stacking fault originally contained in the wafer or produced in the wafer through the thermal oxidation of the wafer surface is subjected to an annealing treatment in a non-oxidative atmosphere to eliminate the stacking fault. A PN junction is thereafter formed in an area of the wafer from which the stacking fault is eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.