Muting arrangement for AM synchronous detector using a PLL circuit
US4117406A · kind A · utility
10Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1977 |
| Grant date | Sep 26, 1978 |
| Priority date | — |
| Expiry date | Mar 29, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/341
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The output voltage of an AM synchronous detector is compared with a reference potential level by a voltage comparator. A muting device connected with the output of the detector is controlled by a control circuit connected with the comparator. Through this control circuit, the detector output is immediately muted when the detector output level falls below the reference potential level, and the muting of the detector output is removed after a predetermined retardation when the detector output level exceeds the reference potential level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.