Diode formed in integrated-circuit structure
US4117507A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 1977 |
| Grant date | Sep 26, 1978 |
| Priority date | — |
| Expiry date | Jun 20, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/619
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC chip with a substrate 10 of one conductivity type (P), overlain by an epitaxially grown layer 12 of the opposite conductivity type (N), includes a diode formed in part by a region 16 of that layer separated from other such isolated regions by a barrier 14 of the first conductive type (P), the remainder of the diode being constituted by an insular central zone 18 of the first conductivity type (18) within that region. To minimize leakage losses when the diode is forwardly biased, a low-resistance zone 22, 32 of the second conductivity type (N+) is interposed between the central zone 18 and the barrier 14, joining a buried low-resistance stratum 30 of the same conductivity type (N+) which lies between region 16 and substrate 10. A first diode electrode (anode) 34 is formed by a metallic coating 34 which covers an upper surface of central zone 18 but is in contact, over most of its area, with an annular low-resistance section 36 of the second conductivity type (N+) embedded in that zone to reduce the number of charge carriers (holes) injected into the diode during forward conduction. A second diode electrode (cathode) consists of a metallic coating 24, 24' in contact with the lo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.