Interlaced CCD memory
US4117546A · kind A · utility
7Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1977 |
| Grant date | Sep 26, 1978 |
| Priority date | — |
| Expiry date | Dec 30, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an interlaced serial-parallel-serial (SPS) charge coupled device (CCD) memory with improved clocking. By performing the interlacing as well as the serial-parallel-serial function with only seven clock pulses, less metallurgy and consequently less space per bit on a semiconductor chip is required. By reducing the number of clock requirements, the supporting logic circuitry is simplified permitting a larger portion of the semiconductor chip area to be used for data bit storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.