JFET base junction transistor clamp
US4118640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1976 |
| Grant date | Oct 3, 1978 |
| Priority date | — |
| Expiry date | Oct 22, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A base junction transistor inverter circuit will be driven into the saturation region if the drive current is large enough. In such circumstances, the collector voltage can go below the base voltage and approaches the emitter voltage. A circuit is provided to keep the transistor out of saturation and is comprised of a p-channel field effect transistor (JFET) connected between the base and collector of the junction transistor. The JFET is connected such that when the drive current increases and the junction transistor approaches saturation, the drive current is diverted through the JFET and into the substrate. The same clamp can be implemented by using a pnp junction transistor in combination with an n-channel JFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.