Error correction for signals employing the modified duobinary code
US4118686A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 1977 |
| Grant date | Oct 3, 1978 |
| Priority date | — |
| Expiry date | Sep 6, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/497
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Single errors can be detected and corrected in a signal employing a 3-level modified duobinary code. Error correction is predicated on the concept of maximum likelihood of error for the bit having the maximum departure from normal amplitude (error differential). A converter accepts the modified duobinary signal, decodes the signal to obtain a binary output signal and determines the error differential for each bit. Bits of the binary output signals are temporarily stored in a sequential storage device. The error differential is applied to an input of an error analyzer. An error detector determines if an error has occurred during an error correction interval which interval is established by successive extreme levels of the modified duobinary signal. The error analyzer tracks the location of the bit having the largest error differential during each error correction interval. A plurality of bit correctors, one for each time slot of the sequential storage device, operate in combination with the error detector and the error analyzer to alter the bit having the highest error differential following detection of an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.