Digital phase locked loop tuning system
US4121162A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1976 |
| Grant date | Oct 17, 1978 |
| Priority date | — |
| Expiry date | Jun 14, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J7/065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.