Error detection in digital systems
US4121195A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1977 |
| Grant date | Oct 17, 1978 |
| Priority date | — |
| Expiry date | May 19, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4906
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention relates to error detecting arrangements for digital transmission systems. It is particularly applicable to systems in which the line signals are already arranged in or can be converted into a format resulting in what may be termed constant accumulated disparity signals. In a digital transmission system parity information is included so as to cause a toggle in a repeater to take up a particular state immediately following each parity check. This state will only change when an error occurs, or an odd number of errors. When an error has occurred and the toggle has changed its state the new state becomes the normal state and a further change indicates a further error. No special line code is needed and circuitry in the repeater is kept to a minimum. For a binary system it requires an extra digit to be added at reasonable intervals, e.g. after every 100 bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.