Patent · US Expired

Delay circuit with field effect transistors

US4122361A · kind A · utility

27Cited by

7References

25Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Rainer Clemen · Böblingen, DE
Werner Haug · Thalwil, CH
Robert Schnadt · Eppelheim, DE

Key dates

Filing date	Nov 10, 1976
Grant date	Oct 24, 1978
Priority date	—
Expiry date	Nov 10, 1996

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00195
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.