Memory and control circuit for the memory
US4122531A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1976 |
| Grant date | Oct 24, 1978 |
| Priority date | — |
| Expiry date | Dec 21, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memory plane area; first control lines connected to the second memory plane areas; a first control circuit for selectively driving the control lines to energize the memory cells in the corresponding second memory plane area; a second control line connected to the first memory plane area; and a second control circuit adapted to selectively energize the memory cells of the first memory plane area through the second control line to permit data transfer between the selected memory cell in the first memory plane area and that corresponding memory cell in the second memory area which is energized through the first control line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.