Patent · US Expired

Memory storage array with restore circuit

US4122548A · kind A · utility

7Cited by

1References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Klaus Heuber
Wilfried Klein · Overath, DE
Knut Najmann
Friedrich-Christian Wernicke · Holzgerlingen, DE
Siegfried K. Wiedmann

Key dates

Filing date	Oct 7, 1977
Grant date	Oct 24, 1978
Priority date	—
Expiry date	Oct 7, 1997

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4113
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.