Logical OR circuit for programmed logic arrays
US4123669A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1977 |
| Grant date | Oct 31, 1978 |
| Priority date | — |
| Expiry date | Sep 8, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.