Signal level stabilizer
US4124825A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1977 |
| Grant date | Nov 7, 1978 |
| Priority date | — |
| Expiry date | Sep 21, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/6911
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A signal level stabilizer includes two amplifier stages, each stage having a respective feed-back loop to control its gain. The gains of the amplifiers are varied in response to variations in the level of the input signal to give a substantially constant output signal. At low levels of the input signal the gain of one of the amplifiers only is varied in response to variations of the input signal and at high levels of the input signal the gain of the other amplifier is varied. The amplifiers may be part of a repeater in an optical communications linkage and one of the amplifiers may then be a photodiode and the other a power amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.