Fail-safe or gate
US4125784A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1977 |
| Grant date | Nov 14, 1978 |
| Priority date | — |
| Expiry date | Jul 27, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fail-safe "OR" logic gate circuit which includes at least a first and a second level detector each of which has a voltage breakdown device and an oscillating circuit, a separate resonant tank circuit each of which is tuned to substantially the same frequency and being loosely coupled between each other, an amplifying circuit coupled to the output of each oscillating circuit, and a regulating-rectifying circuit coupled to the output of the amplifying circuit and producing a d.c. output signal when a d.c. input signal causes either or both of the voltage breakdown devices to break down and to exhibit a low impedance for causing the respective oscillating circuits to oscillate and supply a.c. signals to the amplifying circuit for rectification by the regulating-rectifying circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.