Memory overlay linking system
US4126894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1977 |
| Grant date | Nov 21, 1978 |
| Priority date | — |
| Expiry date | Feb 17, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.