Shared memory access control system for a multiprocessor system
US4128881A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1976 |
| Grant date | Dec 5, 1978 |
| Priority date | — |
| Expiry date | Feb 18, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system having a plurality of processors, each of identical construction, each processor is internally equipped with a fixed address supply source which generates a non-unique fixed address for accessing a common memory unit over commonly connected bus lines, and a sequential state indicate signal generator for generating a logic "1" or "0" synchronizing signal when a special condition (for example, interrupt) occurs with respect to the processor. A shared memory access control system for a multiprocessor system, as above described, includes circuitry, external to and associated with at least each processor except for one processor, responsive to the synchronizing signal from its respective processor for modifying the non-unique fixed address from the respective processor so that, as a result, each processor is able to address the common memory over the commonly connected bus lines with a unique fixed address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.