High speed true/complement driver
US4129793A · kind A · utility
6Cited by
9References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1977 |
| Grant date | Dec 12, 1978 |
| Priority date | — |
| Expiry date | Jun 16, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. A pair of enhancement mode/depletion mode inverters connected in cascade configuration serves to generate the true and complement output signals which are isolated from noise at the input line by a symmetric pair of clocked FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.