Low power true/complement driver
US4130768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1977 |
| Grant date | Dec 19, 1978 |
| Priority date | — |
| Expiry date | Aug 31, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (V.sub.DD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.