Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4130864A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1976 |
| Grant date | Dec 19, 1978 |
| Priority date | — |
| Expiry date | Oct 29, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a shared functional unit having access and egress through a plurality of communication channels to several data handling units. The communication channels are multiplexed under control of a priority selection circuit normally arranged as a ladder from highest to lowest priority. Request signals for the various channels are each passed through a respective gate conditioned by a request enable device which is susceptible of being disabled whenever a select signal for that particular channel has been caused to serve the associated handling unit while channels of lower priority have request signals still demanding selection. When the request signal of lowest order at the time has been served, all request enable devices are reset in order to return to full priority selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.