Hierarchially arranged memory system for a data processing arrangement having virtual addressing
US4130870A · kind A · utility
16Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1977 |
| Grant date | Dec 19, 1978 |
| Priority date | — |
| Expiry date | Sep 12, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchially arranged memory system is described for a data processing system having virtual addressing. A three-level working memory is provided, along with an auxiliary memory, in a data processing system containing a secondary buffer between the main memory and a rapid buffer memory. Whereas the main memory contains all actual storage areas, i.e. the memory pages of the inactive processes which were required for the processing period just passed, the actual storage area for the successor process, independent from the operating system, is set independently by its own microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.