Integrated DDC memory with bitwise erase
US4130890A · kind A · utility
73Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 8, 1977 |
| Grant date | Dec 19, 1978 |
| Priority date | — |
| Expiry date | Jun 8, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This relates to a monolithic dual-dielectric cell (DDC) memory array with a DDCFET matrix. The substrate zones of these DDCFETs are inserted into a substrate body having islands for decoder logic and potential selection integrated MISFET circuits. These circuits provide potentials to bitwise write, erase or read the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.