Memory with common read/write data line and write-in latch circuit
US4130900A · kind A · utility
80Cited by
1References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1977 |
| Grant date | Dec 19, 1978 |
| Priority date | — |
| Expiry date | Apr 25, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch circuit is provided on the input side of write-in circuit of a semiconductor memory device which is so formed that a common data line is used for data writing-in and data reading-out. Write-in data read serially into the latch circuit in a word unit is temporarily stored and held, so that the data is written simultaneously into various memory cells for in column units of the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.