Multi-function logic gate with one gate delay
US4133040A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1977 |
| Grant date | Jan 2, 1979 |
| Priority date | — |
| Expiry date | Jun 30, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A class of logic circuits in which different types of current switching logic gates are connected to different nodes of a current summing network for concurrently producing different logic functions of the same input variables. In one embodiment, N single-input current switches forming a threshold logic gate are operated with their inputs parallelling respective ones of an N-input current switch forming an emitter-coupled logic (ECL) OR-gate. An output current of the ECL gate is combined with the out-of-phase output currents of the threshold gate in a first current summing network, comprised of at least two resistors, for producing different logic functions of the signals applied to the N inputs. The in-phase output currents of the threshold gate are supplied to a second summing network for producing still different logic functions of the input signals. The different logic functions produced at the different nodes of the two summing networks may be further combined (e.g. logically OR'ed) to produce predetermined logic functions, such as the FULL ADDER or EXCLUSIVE-OR within approximately one gate delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.