Shift register type memory
US4133043A · kind A · utility
16Cited by
1References
11Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 21, 1977 |
| Grant date | Jan 2, 1979 |
| Priority date | — |
| Expiry date | Nov 21, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register type memory having major and minor loops, wherein the number of bits of the major loop is large enough to permit data of at least two blocks to simultaneously exist in the major loop when one block is constituted of data of bits the number of which is equal to the number of the minor loops, and wherein before a particular block having been transferred out from the minor loops to the major loop is again transferred in to the minor loops after travelling round the major loop, the next block is transferred out from the minor loops to the major loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.