Analog signal delay system and method
US4134029A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1977 |
| Grant date | Jan 9, 1979 |
| Priority date | — |
| Expiry date | Apr 29, 1997 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog signal delay system is provided with a bucket-brigade charge transfer device controlled by a clock which supplies pulses at a predetermined frequency to sample an analog signal at its input and to effect a predetermined delay between the signal at the input and the corresponding signal at the output. Analog signals are impressed on the input of the system and are sampled at a pulse rate which may be one-half the frequency of the clock pulses. Periodic calibration or correction pulses are supplied to the brigade device during the intervals between the sampling pulses of the analog signal. One or more amplifiers are provided between the output of the brigade device and the output of the system. In order to correct for D.C. drift errors and gain variations which may result from temperature changes, the correction pulses are compared to a reference to generate error signals which are fed to control circuits to correct the D.C. level and gain. This effects the accurate reproduction of the delayed signals in the conformation of the corresponding input signals. The correction pulses are removed from the signal output of the system by gating techniques into an output capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.