Wiring substrate for a matrix circuit
US4136356A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1977 |
| Grant date | Jan 23, 1979 |
| Priority date | — |
| Expiry date | Aug 12, 1997 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wiring substrate for a matrix circuit constituted by mounting a plurality of semiconductor chips in a multi-chip configuration, in which wiring conductors for interconnecting terminal electrodes of the individual chips and terminals of incoming and outgoing lines of the matrix circuit consist of first wiring conductors each for interconnecting the terminal electrodes of adjacent two chips and second wiring conductors for interconnecting the first wiring conductors at their middle portions, whereby the wiring lengths of the wiring conductors through any chips are made substantially equal to one another, thereby to establish uniform resistance among the wiring conductors for the chips with the width of the wiring conductors maintained constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.